| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B20-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49866
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C17-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-498
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-525
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 |
| filingDate |
2018-04-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cfb02f758bbd9040d5e18bc10ba07859
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d3cfc15b6b9770c53cb4694a52252153
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bb11cf89317138867a08528b9a81b90a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c29d5e3f5457120567bb44e5557918ee
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be48afa0ce863757b4b68b22b1bc89b3 |
| publicationDate |
2022-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11264317-B2 |
| titleOfInvention |
Antifuse memory arrays with antifuse elements at the back-end-of-line (BEOL) |
| abstract |
Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11515251-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019304906-A1 |
| priorityDate |
2018-04-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |