| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3237 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0818
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-1565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-135 |
| filingDate |
2021-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa7206862ea12ab0bf80d3b8ddd2412a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_df4dcf1604db32b3af52f0de35d81a87 |
| publicationDate |
2022-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11256285-B2 |
| titleOfInvention |
Clock generation circuit and semiconductor apparatus using the clock generation circuit |
| abstract |
A clock generation circuit may include a clock receiver, a first delay loop circuit, and a second delay loop circuit. The clock receiver may receive a first clock signal and a second clock signal and generate a first reception clock signal and a second reception clock signal. The first delay loop circuit may receive the first reception clock signal and the second reception clock signal generate a reference clock signal. The first delay loop circuit may perform a delay-locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop circuit may delay the first reception clock signal and the second reception clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023090949-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11688442-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022328081-A1 |
| priorityDate |
2020-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |