| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_60e66be87630d7cef0ce770e1d898eec |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42312
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78642 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7391
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78648
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42384
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66977 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 |
| filingDate |
2019-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e26ff7fbab445928a0ae9d57fb713116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f36b2ceb841f8a4736a8426a5fb5759 |
| publicationDate |
2022-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11233131-B2 |
| titleOfInvention |
Tunnel field-effect transistor and method for designing same |
| abstract |
[Problem] To improve the drain current ON/OFF ratio characteristics.[Solution] A tunnel field-effect transistor 10 of the present invention is such that, when the gate length is denoted by LG and the extension distance of a source region 1 extended toward a drain region 3 from a position in the source region 1 is denoted by LOV, LTG expressed in Formula (1) below as the shortest distance between the position of an extension end of the source region 1 based on a drain-side reference position as the side face position of a gate electrode 6a, 6b closest to the drain region 3, and the position in the semiconductor layer 4 opposite to the drain-side reference position in the height direction of the gate electrode 6a, 6b satisfies a condition of Inequality (2) below. Note that lt_OFF in Inequality (2) denotes a shortest tunnel distance over which carriers move from the source region to a channel region through a tunnel junction surface in an OFF state of the tunnel field-effect transistor. |
| priorityDate |
2018-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |