Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b2d32a1324eb3a240649ffee8d475d63 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2007 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-762 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48 |
filingDate |
2020-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2022-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e99682c4e117a8c8b97bbd63db9603cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3ae8faf2eb585a51653469b1518cb1b5 |
publicationDate |
2022-01-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11217525-B1 |
titleOfInvention |
Semiconductor structure and method of forming the same |
abstract |
A semiconductor structure includes a first wafer, a conductive via, an isolation layer, and a spacer structure. The first wafer includes a semiconductor substrate, a multi-level interconnect structure, and a dielectric layer. The semiconductor substrate has a front side and a back side. The multi-level interconnect structure is disposed over the front side of the semiconductor substrate. The dielectric layer is disposed over the back side of the semiconductor substrate. The conductive via extends from the dielectric layer to a conductive line of the multi-level interconnect structure. The isolation layer is disposed between the conductive via and the first wafer. The spacer structure is disposed between the conductive via and the isolation layer, in which the spacer structure is spaced apart from the conductive line. |
priorityDate |
2020-07-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |