Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66553 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7827 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823885 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08 |
filingDate |
2019-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2021-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b90232432b1b2a1f0cdb01aa84d55af9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ff5fdd76cb14e20e49589d29bc268ba http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05f1f86d9fa7250567755f12c7d0d53 |
publicationDate |
2021-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11183581-B2 |
titleOfInvention |
Vertical field effect transistor having improved uniformity |
abstract |
A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins. |
priorityDate |
2019-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |