Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28008 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-516 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7851 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40111 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78391 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-51 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 |
filingDate |
2019-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2021-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6ab5de3c839189e82e3925ba9f41ae69 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0ccb3296e88802fb54c2fbaed9fb00dc http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ae1ab45fceb3d026840bba36b06c4b03 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_afe2716f5f3ed8d1530c91a6d6d24f31 |
publicationDate |
2021-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11152508-B2 |
titleOfInvention |
Semiconductor device including two-dimensional material layer |
abstract |
A semiconductor device including a 2D material layer disposed between a gate electrode and a substrate and a method of forming the same are disclosed. In an embodiment, a device includes a ferroelectric dielectric layer disposed over and in contact with a semiconductor substrate, the ferroelectric dielectric layer including a 2D material; a gate electrode disposed over the ferroelectric dielectric layer; and source/drain regions disposed on opposite sides of the gate electrode. |
priorityDate |
2019-08-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |