| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b6caea61bfde8a45e01a8deabff80d97 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-4401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-76 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-44 |
| filingDate |
2020-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4b3e53826d8936024388baea4fbf54a4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1ff488a36a9409642c9be6fa1822b419 |
| publicationDate |
2021-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11152079-B2 |
| titleOfInvention |
Circuits and methods for reliable replacement of bad columns in a memory device |
| abstract |
An apparatus includes nonvolatile memory cells arranged in columns including a plurality of redundant columns with control circuits coupled to the nonvolatile memory cells. The control circuits are configured to maintain an ordered list of bad columns replaced by redundant columns. The control circuits are configured to detect an out-of-order entry in the ordered list of bad columns replaced by redundant columns. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11735288-B1 |
| priorityDate |
2020-03-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |