Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7202 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1041 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0604 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0679 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0655 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-061 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 |
filingDate |
2019-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2021-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8fe08d2f7ced7ee23c438917e885b502 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1522b044d9c71df9b584fd3ad393f6cc http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_555ea931eff4e1ac7d8699d3c73dc0aa http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cff49e42a77c5736245defc394760e92 |
publicationDate |
2021-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11119692-B2 |
titleOfInvention |
Storage device having wide input/output and method of operating the same |
abstract |
A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted. |
priorityDate |
2018-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |