Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11565 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11573 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344 |
classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11565 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11573 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 |
filingDate |
2019-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2021-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_13d025559edc2387314189acef1872b3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05f1f86d9fa7250567755f12c7d0d53 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb |
publicationDate |
2021-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11107827-B2 |
titleOfInvention |
Integration of split gate metal-oxide-nitride-oxide-semiconductor memory with vertical FET |
abstract |
Embodiments of the present invention are directed to techniques for integrating a split gate metal-oxide-nitride-oxide-semiconductor (SG-MONOS) memory with a vertical field effect transistor (VFET). In a non-limiting embodiment of the invention, a vertical SG-MONOS memory device is formed on a first region of a substrate. The SG-MONOS memory device can include a charge storage stack, a memory gate on the charge storage stack, and a control gate vertically stacked over the charge storage stack and the memory gate. A VFET is formed on a second region of the substrate. The VFET can include a logic gate. |
priorityDate |
2019-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |