| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9047b16961c0aee78d7de367969339b2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3058
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1668
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3062
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-3037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F11-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 |
| filingDate |
2019-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_be26ce4a10d673eba13bebce0f0f44f0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9e7d2fd1fd06fc112c36d7172846bb56 |
| publicationDate |
2021-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11086744-B2 |
| titleOfInvention |
Memory system |
| abstract |
A memory system includes a first memory chip, and a controller that includes a first circuit, a second circuit, and a third circuit. The third circuit is configured to manage a first differential power consumption value that is a difference between first and second power consumption values. The first power consumption value is on first power that the first memory chip consumes while executing a first operation. The second power consumption value is on second power that the first memory chip consumes when suspending the first operation. The third circuit is configured to determine whether causing the first memory chip to suspend the first operation to execute a second operation is possible based on the first differential power consumption value. |
| priorityDate |
2019-01-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |