http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11070218-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0e433c1625fc509a087c912b440da84b |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-181 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0992 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-18 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-07 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-099 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-181 |
| filingDate | 2020-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8073ea57ca49471562e7f16650228031 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_43fc9232bcd8ac58dd2132f29ae4c248 |
| publicationDate | 2021-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-11070218-B2 |
| titleOfInvention | Real time counter-based method for the determination and measurement of frequency lock time in phase-locked loops |
| abstract | A system to test a PLL circuit driven by a reference clock includes a first counter coupled to a reference clock output, a first buffer coupled to the first counter, a second counter coupled to a controlled-oscillator (CO) output of the PLL circuit, a second buffer coupled to the second counter, and a processor configured to compute a PLL lock time according to second count values in the second buffer, and to compute a PLL startup slope according to the first count values in the first buffer and the second count values in the second buffer. A method includes powering up a PLL circuit of a wafer, sampling count values of a reference clock and second count values of the PLL circuit and computing a PLL performance parameter according to the sampled count values in a buffer. |
| priorityDate | 2019-04-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 44.