Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32134 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823807 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0274 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823828 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823857 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3213 |
filingDate |
2020-02-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2021-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d4b59591702a81117b1c5a3de6ce1bd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_98e57eb562f81eba6587528a556712a3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2897cb9a88c1f2b9c079c00f7da228d0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5d8147bdd6f73c707f8a594dbc72a87b |
publicationDate |
2021-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-11069580-B2 |
titleOfInvention |
Method of manufacturing a semiconductor device including a plurality of channel patterns |
abstract |
A semiconductor device manufacturing method includes forming a gate dielectric layer surrounding first semiconductor patterns and second semiconductor patterns; forming a first organic pattern covering the second semiconductor patterns; forming a sacrificial pattern interposed between the first semiconductor patterns and exposing both side surfaces of the first semiconductor patterns, and a conductive pattern surrounding the second semiconductor patterns and disposed between the first organic pattern and the second semiconductor patterns; forming a second organic pattern covering the first semiconductor patterns, the gate dielectric layer, the sacrificial pattern, and the first organic pattern; and forming a cross-linking layer interposed between the first organic material pattern and the second organic material pattern. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2023026989-A1 |
priorityDate |
2019-07-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |