| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9047b16961c0aee78d7de367969339b2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5671 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-025
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-18 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08 |
| filingDate |
2018-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ef0ae6be953397760bf4449ce9179fb |
| publicationDate |
2021-06-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11037634-B2 |
| titleOfInvention |
Semiconductor storage device having a group adjacent bit lines connected to sense circuits that are each connected to a different data bus |
| abstract |
A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction. |
| priorityDate |
2017-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |