| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-201
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02461
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30612
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02546 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-201
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-308
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-306
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 |
| filingDate |
2020-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d2d259b865390527410f2e2865d310b1 |
| publicationDate |
2021-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11031393-B2 |
| titleOfInvention |
III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface |
| abstract |
A semiconductor device that includes a fin structure of a type III-V semiconductor material that is substantially free of defects, and has sidewalls that are substantially free of roughness caused by epitaxially growing the type III-V semiconductor material abutting a dielectric material. The semiconductor device further includes a gate structure present on a channel portion of the fin structure; and a source region and a drain region present on opposing sides of the gate structure. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11776956-B2 |
| priorityDate |
2016-02-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |