| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76852
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76852
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7688
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76829
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2016-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5b6e15cdb4330d46da11915e4513a23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a86dfb649bada6d786c2f7c9502b577
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93b6dfd4eb03ac01752a05cfe7f73da8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4f9c0fad56061cfa609480b42a4dcb49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_65f79bdba5d00a8e09f5c6ede377182f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e8602c523f55b20ac5145dcf9616141 |
| publicationDate |
2021-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11024538-B2 |
| titleOfInvention |
Hardened plug for improved shorting margin |
| abstract |
In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect. |
| priorityDate |
2016-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |