| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_23a4e0c875bf1ac2b8a3b76517de6c7d |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-419
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4094 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4094
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-419
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4091 |
| filingDate |
2020-02-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_302a682d4b044eba3c30d5a41b362255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_002d4daaae58179387cadb476c3e6e92 |
| publicationDate |
2021-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11024348-B2 |
| titleOfInvention |
Memory array with reduced read power requirements and increased capacity |
| abstract |
An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain. |
| priorityDate |
2015-05-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |