| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6681
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2019-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5ff5fdd76cb14e20e49589d29bc268ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d05f1f86d9fa7250567755f12c7d0d53
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b90232432b1b2a1f0cdb01aa84d55af9 |
| publicationDate |
2021-05-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-11011626-B2 |
| titleOfInvention |
Fin field-effect transistor with reduced parasitic capacitance and reduced variability |
| abstract |
A method for manufacturing a semiconductor device includes patterning a plurality of semiconductor fins on a semiconductor substrate, and replacing at least two of the plurality of semiconductor fins with a plurality of dummy fins including a dielectric material. A gate structure is formed on and around the plurality of semiconductor fins and the plurality of dummy fins, and a source/drain contact is formed adjacent the gate structure. |
| priorityDate |
2019-05-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |