| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-81
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-808 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-808
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-838 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08 |
| filingDate |
2019-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a83ac9dafa4abc2f872c79541b3e4eda
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_19e170c88796da27a91797d5be316420 |
| publicationDate |
2021-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10984868-B1 |
| titleOfInvention |
Redundancy in microelectronic devices, and related methods, devices, and systems |
| abstract |
Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed. |
| priorityDate |
2019-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |