| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bc905cbef116a1ec61d12125af9427f3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D5-022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-123
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-2885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D5-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-488 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-288
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40 |
| filingDate |
2019-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_282dede7d415466bf6b4192411295881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ff248cd56488c7ae51f391049e10f513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6eb8e834dbbc0935aa2743378bf5894f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4877389d4c6d36e9b4d6994fbe29878e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d5a03d02095dd5a971ad6ab120d9e608
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_04b64b5f60767fbe0d14f9c74d706755 |
| publicationDate |
2021-03-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10941498-B2 |
| titleOfInvention |
Panel to be plated, electroplating process using the same, and chip manufactured from the same |
| abstract |
A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3. |
| priorityDate |
2018-08-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |