| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-5002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0403
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-048 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-54
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-037 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06N3-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 |
| filingDate |
2019-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00493c8d5b956f1a1dbffaf60e57a6c7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aa07e0c99c24a951a9ae29a1ca0eb12f |
| publicationDate |
2021-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10924090-B2 |
| titleOfInvention |
Semiconductor device comprising holding units |
| abstract |
A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11057226-B1 |
| priorityDate |
2018-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |