| abstract |
A three-dimensional memory device includes a source-level material layer stack located over a substrate that includes, from bottom to top, a lower source-level semiconductor layer, a semiconductor oxide tunneling layer, a source contact layer including a doped semiconductor material, and an upper source-level semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the source-level material layer stack, and memory stack structures that extend through the alternating stack and into an upper portion of the lower source-level semiconductor layer, in which each memory stack structure includes a vertical semiconductor channel and a memory film laterally surrounding the vertical semiconductor channel, and each of the vertical semiconductor channels vertically extends through, and is electrically connected to, the source contact layer. |