| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_099413ae0cf5a2b6398b5151766cd260 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2330-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0291
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0267
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2300-0413
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0243
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0275
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-08 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3674 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G5-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 |
| filingDate |
2019-08-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e2f19f2189a87083d1746aca6c4157e8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a7d81126df254ce37413aab693e376f7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed7eb446d3b6de6273d413ea2caa1067
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8b9cdb373031802327de27c1a66178f1 |
| publicationDate |
2021-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10909897-B2 |
| titleOfInvention |
Gate driving circuit and display device having the same |
| abstract |
A gate driving circuit includes a shift register configured to generate a plurality of output signals based on at least one clock signal, a plurality of output buffers configured to generate a plurality of gate signals by amplifying the output signals and to sequentially output the gate signals to a plurality of gate lines in a display panel, a detector configured to sequentially sense the gate signals and to compare each of the gate signals to a reference voltage, and a dummy output buffer configured to be coupled between the shift register and a gate line of the gate lines instead of an output buffer of the output buffers when a voltage level of a corresponding gate signal from the output buffers is less than a voltage level of the reference voltage. |
| priorityDate |
2018-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |