| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9047b16961c0aee78d7de367969339b2 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-12 |
| filingDate |
2019-09-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3345721132cef8f841ce646ef9eebfbb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_512fcee44486308defbae9a7528c383d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f06538912f1c4c33e9b8995b6462665a |
| publicationDate |
2021-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10896735-B2 |
| titleOfInvention |
Semiconductor memory device |
| abstract |
According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11705210-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11257551-B2 |
| priorityDate |
2018-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |