| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1104
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-10873
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B10-12 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76256
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66772 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2019-05-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8b4aa2696163f6944d3c7d8b925a2975 |
| publicationDate |
2020-12-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10867837-B2 |
| titleOfInvention |
Methods of forming integrated circuitry |
| abstract |
Some embodiments include methods in which a structure has a first semiconductor material over a dielectric region, a second semiconductor material under the dielectric region, an insulative wall laterally surrounding a volume of the first semiconductor material, and a first doped region along a lower surface of the first semiconductor material. The first semiconductor material is patterned to form a pillar within a tub. The pillar has top and bottom portions. An upper doped region is formed within the pillar top portion. A dielectric liner is formed to extend along the pillar, and to extend along the bottom of the tub. Conductive gate material is formed within the tub and over the dielectric liner. The lower and upper doped regions within the pillar are first and second source/drain regions, respectively, and the conductive gate material includes a transistor gate which gatedly couples the first and second source/drain regions. |
| priorityDate |
2017-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |