| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_23a4e0c875bf1ac2b8a3b76517de6c7d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-18 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30036
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1675
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3004 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-18 |
| filingDate |
2019-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6d33009cfff6764b9d2b527c42bf9a00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6a1ebaa5eb081cc977730eee8368a051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1af52cace56213480505d2bae2e3d6c6 |
| publicationDate |
2020-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10802827-B2 |
| titleOfInvention |
Memory device having in-situ in-memory stateful vector logic operation |
| abstract |
An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11250896-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11514963-B2 |
| priorityDate |
2018-02-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |