| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_3190cca5617873b5eb2bcbaee9795542 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-05 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-36125
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/A61N1-025 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-05
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-66 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A61N1-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A61N1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A61N1-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/A61N1-05 |
| filingDate |
2017-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d3f8b51b0d3bbfc1eac58911cd0b723f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_38e8093ffc1b81528b9dd7e2301f3d4e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_92cd982547cafdcf8d7154aadd0f14a8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_741f694b46639ef7df4783d635ca47f1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d7bc66aee0071c723b2d4340bdf874dc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a751bb2262d369af214ed61e6b4c68ee |
| publicationDate |
2020-09-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10786665-B2 |
| titleOfInvention |
Biasing of a current generation architecture for an implantable medical device |
| abstract |
Digital-to-analog converter (DAC) circuitry for providing currents at electrodes of an Implantable Pulse Generator (IPG) is disclosed. The DAC circuitry includes at least one PDAC for sourcing current to the electrodes, and at least one NDAC for sinking current from the electrodes. The PDACs are powered with power supplies VH (the compliance voltage) and Vssh in a high power domain, and the NDACs are powered with power supplies Vcc and ground in a low power domain. VH may change during IPG operation, and Vssh preferably also changes with a fixed difference with respect to VH. Digital control signals to the PDACs are formed (and possibly converted into) the high power domain, and transistors used to build the PDACs are biased in the high power domain, and thus may also change with VH. This permits transistors in the PDACs and NDACs to be made from normal low-voltage logic transistors. |
| priorityDate |
2016-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |