http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10770126-B2

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http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22
filingDate 2019-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06d5d4cd8045fcaefc6e37ef7059fad6
publicationDate 2020-09-08-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10770126-B2
titleOfInvention Parallel access techniques within memory sections through section independence
abstract A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to memory cells within independent sections of the memory device. A first memory cell may be activated, and it may be determined that a second memory cell is independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated prior to the conclusion of operations at the first memory cell. Latching hardware at memory sections may latch addresses at the memory sections in order to allow a new address to be provided to a different section to access the second memory cell.
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Total number of triples: 25.