| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6681
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762 |
| filingDate |
2019-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_576377a10d95df2d7aa66f99abc323f3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_efdfe150d51fb48b73bf965f96c3eae1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af9b0ed5c62cb9c10030aa1e961f620f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b760d1cbb18c6ade1b5a0fa346ba2290
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68298e8e373a8c0ab442b9ee65fd5848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4174a4963ddd9123dac4d9324aabff9 |
| publicationDate |
2020-08-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10749014-B2 |
| titleOfInvention |
Method and structure for FinFET comprising patterned oxide and dielectric layer under spacer features |
| abstract |
A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer. The semiconductor device further includes a second dielectric layer vertically between the first dielectric layer and the gate spacer, wherein the first and second dielectric layers include different materials, and wherein the second dielectric layer is in physical contact with the gate spacer and the first dielectric layer. |
| priorityDate |
2014-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |