| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fa80eed27901ac84139c7a7109c21e17 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2933-0016
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-1403
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-325
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-62
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L33-38 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-40 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-62
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-44
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L33-00 |
| filingDate |
2018-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_582ed222210aa4b660c2b59567954280
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_07377e537887070a577fc2069b9ba2ca |
| publicationDate |
2020-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10734550-B2 |
| titleOfInvention |
Semiconductor device |
| abstract |
Disclosed herein is a semiconductor device including: a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulating layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer through a first hole of the first insulating layer; a second electrode disposed on the second conductive semiconductor layer through a second hole of the first insulating layer; a first cover electrode disposed on the first electrode; and a second cover electrode disposed on the second electrode, wherein the second cover electrode includes a plurality of pads, and a connecting portion configured to connect the plurality of pads, a width of the connecting portion is smallest at a central position between the adjacent pads, and an area ratio between the second cover electrode and the first cover electrode is in the range of 1:1.1 to 1:1.5. |
| priorityDate |
2017-08-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |