| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6653
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417 |
| filingDate |
2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_337c73316e986c8c90bc56901d0a2631
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_83150856a4246f8b51b62b79bf699223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e08d91ff19fce642276d4cd68e163970 |
| publicationDate |
2020-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10734477-B2 |
| titleOfInvention |
FinFET with reduced parasitic capacitance |
| abstract |
A semiconductor device including at least one fin extending upward from a substrate and a gate on the substrate, wherein the gate includes outer sidewalls, wherein the fin extend through a width of the gate. A spacer material can be adjacent to the outer sidewalls of the gate, wherein a top surface of the spacer material is below the top surface of the gate and above the top surface of the fin. The semiconductor device can also include an epitaxial semiconductor layer over the fins on each side of the spacer material. A low-k dielectric material can be deposited above each epitaxial semiconductor layer. The semiconductor device also includes a dielectric top layer forming a top surface of the transistor, wherein the dielectric top layer seals an air gap between the top surface of the fins and the dielectric top layer. |
| priorityDate |
2015-12-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |