Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-049 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-063 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-2481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1683 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1608 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-249 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-066 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L45-1233 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06N3-063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24 |
filingDate |
2018-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate |
2020-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dce47eb6932fa56b7d1ab8fad62751ba http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b71ed8d1014ded9f660a7efc37fd1c00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_15c31ac78394568dea434cbc69f28a69 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fa57155a94ec485068066724e7721ca7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac3c9365ac185348d99c5460aa0b0e23 |
publicationDate |
2020-08-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
US-10734447-B2 |
titleOfInvention |
Field-effect transistor unit cells for neural networks with differential weights |
abstract |
Techniques regarding FET 1T2R unit cells are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a first resistive random-access memory unit operably coupled to a field-effect transistor by a first extrinsic semiconductor layer. The system can also comprise a second resistive random-access memory unit operably coupled to the field-effect transistor by a second extrinsic semiconductor layer. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2020365698-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10879308-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11069784-B2 |
priorityDate |
2018-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |