| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_283357e4e5b1d2334bd15817360ddd5a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0401 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2607
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-12015
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-2882
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-50012
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G01R31-31726 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-04 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-317
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-50 |
| filingDate |
2019-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d67257f4f4beb55c423d571a0521b87a |
| publicationDate |
2020-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10725099-B2 |
| titleOfInvention |
Memory controller with integrated test circuitry |
| abstract |
A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2021248094-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11789644-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11580038-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11675500-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11561911-B2 |
| priorityDate |
2011-03-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |