| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y25-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y40-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-161 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B82Y25-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-16 |
| filingDate |
2018-04-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d743fc01f452029a52301a4783eaa430
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed36611f5c9716769d64ba58efa4cf79
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3498cddc20572753bf882a366e80646e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6081b3beb2159d6ae89fa4ef646165cd
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b381ffa2f7a76dfda956c5a57f65468f |
| publicationDate |
2020-06-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10680168-B2 |
| titleOfInvention |
Ion beam etching fabricated sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices |
| abstract |
A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device. |
| priorityDate |
2018-04-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |