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filingDate 2018-06-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97a1512d12f7f6841bf1971735b66000
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publicationDate 2020-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10672710-B2
titleOfInvention Interconnect structures with reduced capacitance
abstract The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.
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