| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5066 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-7867
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17756
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-4881
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-52 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-50 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-17756
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F30-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-48 |
| filingDate |
2017-09-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e0cad29f46cd1b724c0035c460f1ed44 |
| publicationDate |
2020-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10671429-B2 |
| titleOfInvention |
Circuit assignment within reconfigurable device based on predicted shortest processing completion time |
| abstract |
An information processing apparatus includes: a reconfiguration device which can change a circuit configuration through a dynamic partial reconfiguration; and a controller which controls a circuit arrangement in the reconfiguration device, in which when a processing circuit related to a new task is arranged in the reconfiguration device, the controller determines a circuit assignment of a processing circuit related to an existing task in execution and the processing circuit related to the new task with respect to an area as a result of combining an area used for the processing circuit related to the existing task in execution and a space area, based on a predicted end time of the processing of the respective tasks, and arranges the processing circuits related to the respective tasks in the reconfiguration device in accordance with the determined circuit assignment. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2022004400-A1 |
| priorityDate |
2016-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |