| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4b4737cc0e657a11b7126a01e2059498
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4e75705563513024d73283917d022a7d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823892
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66712
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7803
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0878
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1083
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823493
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41758
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2017-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_30d383afe39844d2122f341abfdb4b3f |
| publicationDate |
2020-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10658464-B2 |
| titleOfInvention |
MOS transistor for radiation-tolerant digital CMOS circuits |
| abstract |
A monolithically integrated MOS transistor, comprising a doped well region of a first conductivity type, an active MOS transistor region formed in the well region, comprising doped source and drain regions of a second conductivity type and at least one MOS channel region extending between the source and drain regions under a respective gate stack, and a dielectric isolation layer of the STI or LOCOS type and laterally surrounding same, wherein well portions of the well region adjoin the MOS channel region in the two opposite longitudinal directions oriented perpendicular to a notional connecting line extending from the source through the MOS channel region to the drain region, and which extend as far as a surface of the active MOS transistor region, so that the respective well portion adjoining the MOS channel region is arranged between the MOS channel region and the dielectric isolation layer. |
| priorityDate |
2016-05-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |