| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_8d0fc2b70675ee19bd5fc464f5ae9061 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5614 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1675
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1655
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-147
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1006
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1697 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-39
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L43-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate |
2019-01-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-04-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4f70b00c621e506415309469501b46a7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da57d55bc70c511e18ac6c3737b49ff4 |
| publicationDate |
2020-04-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10636467-B2 |
| titleOfInvention |
SOT-MRAM and method for writing data thereof |
| abstract |
A semiconductor device includes a line driving unit connected to a memory cell array, a switch unit including first and second output terminals electrically connected to the memory cell array through a plurality of bit lines and a plurality of source lines, and a power supply unit outputting a precharge voltage and a source voltage to the first and second output terminals. The power supply unit includes a negative voltage generation unit that charge-shares the precharge voltage to be charged with a first voltage and discharges the first voltage to one side to generate a negative voltage on the other side. |
| priorityDate |
2018-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |