| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_51d028c578ae85cb937b5b34a5129fbc |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1052
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L2209-12 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-0631
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-1408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-72
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-3093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09C1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09C1-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-72
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L9-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L9-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-00 |
| filingDate |
2018-01-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9227c138a6f245fa63e6ededb5417c3e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c4336f106f095c2176f5d664306503ef
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fb654c27be2044be43320562f037b7a1 |
| publicationDate |
2020-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10606765-B2 |
| titleOfInvention |
Composite field scaled affine transforms-based hardware accelerator |
| abstract |
A cryptographic hardware accelerator identifies a mapped input bit sequence by applying a mapping transformation to an input bit sequence retrieved from memory and represented by a first element of a finite-prime field. The mapped input bit sequence is represented by a first element of a composite field. The accelerator identifies a mapped first key by applying the mapping transformation to an input key represented by a second element of the finite-prime field. The mapped first key is represented by the second element. The accelerator performs, within the composite field, a cryptographic round on the mapped input bit sequence using the mapped first key during a first round of the at least one cryptographic round, to generate a processed bit sequence. The accelerator identifies an output bit sequence to be stored back in the finite-prime field by applying an inverse mapping transformation to the processed bit sequence. |
| priorityDate |
2016-04-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |