| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_af4cc10d515454e59278de7445531247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0ab4ca6e227a4118ad7f1d947eb01713 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02238
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02529 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02595
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate |
2018-05-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_451b7faf3bcb48c5e94ea57d2febb830
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e48f04d0e5c4220fe649db0b1de742b0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8f982ff9784bda05e1185cd61a990959
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fe4dcc43de77561be4a30438e85a0c79
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_57fc26a1b23471d19d39a0f595a311d6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c22996a27376fac266a996ded09cac2a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7447ed6352616e1babf8639f47daa313
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a758fd8bb25126ce8926846b60e66506 |
| publicationDate |
2019-08-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10381261-B2 |
| titleOfInvention |
Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers |
| abstract |
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer. |
| priorityDate |
2014-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |