| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-516
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28194
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-085
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-085 |
| filingDate |
2017-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac3c9365ac185348d99c5460aa0b0e23
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4709a4440900179fe6555ddcbf4e678
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c539cdc4e52be2e966028227aeed4a42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ee3cbdb66f4e215e6f59e6aab222e8c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_18bd5a8f122e2d33d662a40e667049fd |
| publicationDate |
2019-06-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10319818-B2 |
| titleOfInvention |
Artificial synapse with hafnium oxide-based ferroelectric layer in CMOS front-end |
| abstract |
Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-2019252499-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10686039-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10686040-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11688457-B2 |
| priorityDate |
2017-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |