| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_68902f46d31f7b540653a398ef6058c3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-481 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-4824
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4022
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-4282
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-504
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-525 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-504
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-525
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-48 |
| filingDate |
2017-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b07822a3d9f96800ff0867d4bb8f51de
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_299dfb9df312ca164e28464968b909bb |
| publicationDate |
2019-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10275219-B2 |
| titleOfInvention |
Bit-serial multiplier for FPGA applications |
| abstract |
A Field-Programmable Gate Array (FPGA) implementation of a multiplier topology can provide a considerable increase in computation performance and cost benefit as compared to other approaches, particularly for large bit widths (e.g., for multiplication of large-bit numbers). A lack of sufficient input/output (I/O) ports on the FPGA for a particular bit width can be remedied by implementing large-bit number multiplications in a bit-serial fashion. The bit-serial multiplier topologies described herein can provide a relatively small footprint as compared to other approaches. An FPGA-implemented bit-serial multiplier can improve operation of a computing system, for example, by offloading binary multiplication operations from a general-purpose processor. |
| priorityDate |
2016-11-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |