| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4085 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-017
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K3-0372 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-408
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4074 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-20 |
| filingDate |
2017-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f23a4de448f93d7dc7b83bcaa9792677
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72067edcf34f9ce707d73bb44ec5d99e |
| publicationDate |
2019-04-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10270431-B2 |
| titleOfInvention |
Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times |
| abstract |
Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal. |
| priorityDate |
2017-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |