| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-13067
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0645 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0676 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate |
2017-10-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2019-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b216a1fbec3e4bdacbad393880bc2188
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9109b68b55594387713c374f294c46cb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_066347c3f9029648fe458818b87f86e0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a05d3ae07542da0d1e6b0de10ca3b8bc |
| publicationDate |
2019-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10242983-B2 |
| titleOfInvention |
Semiconductor device with increased source/drain area |
| abstract |
A semiconductor device includes a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, and a spacer arranged adjacent to the gate stack. A source/drain region is arranged in the fin the source/drain region having a cavity that exposes a portion of the semiconductor fin. An insulator layer is arranged over a portion of the fin, and a conductive contact material is arranged in the cavity and over portions of the source/drain region. |
| priorityDate |
2016-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |