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filingDate 2015-09-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2019-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_35619b9d41976cc19caee4834402217f
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publicationDate 2019-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10217860-B2
titleOfInvention Partially biased isolation in semiconductor devices
abstract A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate and defining a core device area within the doped isolation barrier, an isolation contact region disposed in the semiconductor substrate outside of the core device area and to which a voltage is applied during operation, and a depleted well region disposed in the semiconductor substrate outside of the core device area. The depleted well region electrically couples the isolation contact region and the doped isolation barrier such that the doped isolation barrier is biased at a voltage level lower than the voltage applied to the isolation contact region.
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