http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10133686-B2
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca160f9d26e9c4312152e7569156d267 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1657 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1673 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-36 |
| filingDate | 2014-06-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2018-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8badcd73e35ec4b4a3c294d4ba4794f6 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52e6fc2a751eaa2e5ef7d9b54eda2649 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d3989454a96e19b375556d5ced0469e |
| publicationDate | 2018-11-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | US-10133686-B2 |
| titleOfInvention | Multilevel memory bus system |
| abstract | The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these. |
| priorityDate | 2009-09-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 53.