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filingDate 2015-09-24-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2018-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10103877-B2
titleOfInvention SMS4 acceleration processors having round constant generation
abstract A processing system includes a memory and a processing logic operatively coupled to the memory. The processing logic identifies one or more constant bits of an output bit sequence. The processing logic generates a plurality of variable bits of the output bit sequence. The processing logic produces the output bit sequence including the identified constant bits and the generated plurality of variable bits.
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