http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10103106-B2

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filingDate 2017-01-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2018-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_42bd5c92c906c83bf8a1f54e45c6f402
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publicationDate 2018-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber US-10103106-B2
titleOfInvention Wafer level fan-out with electromagnetic shielding
abstract The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an input/output (I/O) port at a bottom surface of the die, a mold compound partially encapsulating the die and leaving the bottom surface of the die exposed, a first dielectric pattern over the bottom surface of the die, a redistribution structure over the first dielectric pattern, and a shielding structure. The I/O port at the bottom surface of the die is exposed through the first dielectric pattern. The redistribution structure includes a shield connected element that is coupled to the I/O port and extends laterally beyond the die. The shielding structure resides over a top surface of the mold compound, extends along side surfaces of the mold compound, and is in contact with the shield connected element. Herein, the shielding structure does not extend vertically beyond the shield connected element.
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priorityDate 2015-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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