| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76837 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-401
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31116
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4916
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0617
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76837 |
| classificationIPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 |
| filingDate |
2017-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2018-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0c43145742ca904431bbdd76d4c64cd0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1eab56e85de8e7b4dcfe7c0f90427de7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fc8398cbd65d05613961e9cf273ad3a5 |
| publicationDate |
2018-09-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
US-10084056-B1 |
| titleOfInvention |
Semiconductor structure and method of manufacturing the same |
| abstract |
A method of manufacturing a semiconductor structure is provided. An interlayer dielectric layer is formed conformally over protruding structures formed over a silicon substrate and a surface of the silicon substrate. Next, a vaporized chemical etching operation is performed to the interlayer dielectric layer, so as to form a gap between two adjacent protruding structures. The gap has a target aspect ratio of at least 4, a top portion of the interlayer dielectric layer above an upper portion of each of the at least two protruding structures is trimmed at a first etching rate, and a bottom portion of the interlayer dielectric layer above a base portion of each of the at least two protruding structures is etched at a second etching rate smaller than the first etching rate, for enlarging the deposition process window and preventing voids from remaining inside a gap filling material in the gap. |
| priorityDate |
2017-03-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |