| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b2d32a1324eb3a240649ffee8d475d63 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-165
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6659
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0692
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7848
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-302
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-36 |
| filingDate |
2020-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_75880264aea710411984da064983b36a |
| publicationDate |
2021-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
TW-I749697-B |
| titleOfInvention |
Semiconductor device and method for fabricating the same |
| abstract |
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate, a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate, and a third semiconductor stack having a third threshold voltage and comprising a third insulating stack positioned on the substrate. The first threshold voltage, the second threshold voltage, and the third threshold voltage are different from each other, a thickness of the first insulating stack is different from a thickness of the second insulating stack and a thickness of the third insulating stack, and the thickness of the second insulating stack is different from the thickness of the third insulating stack. |
| priorityDate |
2019-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |