| abstract |
A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric nlayer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed. |